photo

Ronny Krashinsky

ronny [at] alum [dot] mit [dot] edu



Publications:

Many of these papers are copyright of the respective journal or conference organizing body. These online copies are provided for your personal research use only.

  • "Implementing the Scale Vector-Thread Processor"
    Ronny Krashinsky, Christopher Batten, and Krste Asanovic
    ACM Transactions on Design Automation of Electronic Systems, Vol. 13, No. 3, July 2008.
    [ PDF ]

  • "Vector-Thread Architecture and Implementation"
    Ronny Krashinsky
    Ph.D. Thesis, Massachusetts Institute of Technology, June 2007.
    MIT Sprowls Award for best doctoral theses in Computer Science.
    [ PDF ]

  • "The Scale Vector-Thread Processor"
    Ronny Krashinsky, Christopher Batten, and Krste Asanovic
    DAC/ISSCC Student Design Contest Winner, February/June 2007.

  • "Scale Control Processor Test-Chip"
    Christopher Batten, Ronny Krashinsky, and Krste Asanovic
    MIT CSAIL Technical Report, MIT-CSAIL-TR-2007-003, January 2007.
    [ PDF ]

  • "Minimizing Energy for Wireless Web Access with Bounded Slowdown"
    Ronny Krashinsky and Hari Balakrishnan
    ACM/Kluwer Journal on Wireless Networks (WINET), Vol. 11, No. 1-2, pp. 135-148, January 2005.
    (Extended version of MobiCom 2002 paper)
    [ PDF | journal ]

  • "Cache Refill/Access Decoupling for Vector Machines"
    Christopher Batten, Ronny Krashinsky, Steve Gerding, and Krste Asanovic
    37th International Symposium on Microarchitecture (Micro-37), Portland, OR, December 2004.
    [ PDF | conference ]

  • "The Vector-Thread Architecture"
    Ronny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian Pharris, Jared Casper, and Krste Asanovic
    IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, November/December 2004.
    (Abridged version of ISCA 2004 paper)
    [ PDF | magazine ]

  • "The Vector-Thread Architecture"
    Ronny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian Pharris, Jared Casper, and Krste Asanovic
    31st International Symposium on Computer Architecture (ISCA-31), Munich, Germany, June 2004.
    [ PDF | PDF slides | PPT slides | CiteSeer | conference ]

  • "A Scalable Cellular Logic Technology Using Zinc-Finger Proteins"
    Christopher Batten, Ronny Krashinsky, and Thomas Knight, Jr.
    3rd Workshop on Non-Silicon Computing (NSC-03), ISCA-31, Munich, Germany, June 2004.
    [ PDF | PDF slides ]

  • "Minimizing Energy for Wireless Web Access with Bounded Slowdown"
    Ronny Krashinsky and Hari Balakrishnan
    MobiCom 2002, Atlanta, GA, September 2002.
    (Subsequent version published in WINET 2005, see above)
    [ PDF | PDF slides | PPT slides | CiteSeer | conference | simulation code ]

  • "Energy-Exposed Instruction Sets"
    Krste Asanovic, Mark Hampton, Ronny Krashinsky, and Emmett Witchel
    Power Aware Computing, ed. by R. Graybill and R. Melhem, Kluwer Academic/Plenum Publishers, Chapter 5, June 2002.
    [ PDF | book website ]

  • "Multithreading Decoupled Architectures for Complexity-Effective General Purpose Computing"
    Michael Sung, Ronny Krashinsky, and Krste Asanovic
    Workshop on Memory Access Decoupled Architectures (MEDEA'01), PACT'01, Barcelona, Spain, September 2001.
    (Also appears in) Computer Architecture News, 29(5), December 2001.
    [ PDF | CiteSeer | workshop ]

  • "Microprocessor Energy Characterization and Optimization through Fast, Accurate, and Flexible Simulation"
    Ronny Krashinsky
    S.M. Thesis, Massachusetts Institute of Technology, May 2001.
    [ PDF | CiteSeer ]

  • "Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy"
    Seongmoo Heo, Ronny Krashinsky, and Krste Asanovic
    19th Conference on Advanced Research in VLSI, Salt Lake City, UT, March 2001.
    (Abridged version appears in) IEEE Transactions on VLSI Systems, 15(9), September 2007.
    [ PDF | PDF slides | PPT slides | CiteSeer | conference]

  • "SyCHOSys: Compiled Energy-Performance Cycle Simulation"
    Ronny Krashinsky, Seongmoo Heo, Michael Zhang, and Krste Asanovic
    Workshop on Complexity-Effective Design, 27th International Symposium on Computer Architecture, June 2000.
    [ PDF | PDF slides | PPT slides | CiteSeer ]

Class Projects:

  • "The Booperator Project"
    Synthetic Biology Lab: Engineered Genetic Polka Dots, January 2004.
    [ project web-page ]

  • "A Scalable Cellular Logic Technology Using Zinc-Finger Proteins"
    Engineering Simple Biological Systems (6.971), fall 2003.
    (Subsequent version published in NSC Workshop, ISCA 2004, see above)
    [ PDF ]

  • "A Dataflow Execution Core Prototype"
    Introduction to VLSI Systems (6.371), fall 2002.
    [ project web-page | class ]

  • "Maintaining Performance while Saving Energy on Wireless LANs"
    Computer Networks (6.829), fall 2001.
    (Subsequent versions published in MobiCom 2002 and WINET 2005, see above)
    [ PDF | PPT slides | CiteSeer | class ]

  • "Decoupled Architectures for Complexity-Effective General Purpose Processors"
    Advanced VLSI Computer Architecture (6.893), fall 2000.
    (Subsequent version published in MEDEA Workshop, PACT 2001, see above)
    [ PDF | PPT slides | CiteSeer | class ]

  • "Efficient Web Browsing for Mobile Clients using HTTP Compression"
    Distributed Operating Systems (6.894), fall 2000.
    (published as MIT LCS Technical Report, MIT-LCS-TR-882, January 2003)
    [ PDF | CiteSeer | class ]

  • "GRAPE: Genetic Routing And Placement Engine"
    Embodied Intelligence (6.836), spring 2000.
    [ PDF | CiteSeer | class ]

  • "Software Cache Coherent Shared Memory under Split-C"
    Parallel Processors (UC Berkeley CS 258), spring 1999.
    [ PDF | html | PPT slides | CiteSeer | class ]